Lithography is used in various applications for producing patterned structures, for example in the manufacture of integrated circuits, flat panel displays, micro-electro-mechanical systems, micro-optical systems, etc. During manufacture, a substrate typically undergoes a sequence of lithography-etching steps to produce the various features to result in a desired pattern within the uppermost portion of the substrate. The resultant pattern may be analyzed in a non-destructive manner using metrology techniques to determine, for example, placement and/or dimensions of the features or spaces between the features in the pattern, or to determine thickness or other attribute of deposited material.
One example metrology technique is scatterometry which impinges electromagnetic radiation onto a substrate pattern and analyzes spectral characteristics of reflected radiation to determine certain parameters of the pattern. This is done by comparing spectrographic characteristics of the reflected radiation to a theoretical or simulated ideal expectation representing what would have been achieved had perfect deposition, processing, patterning, and spectral analysis occurred. A software modeling process may be used to arrive at the desired theoretical ideal spectral characteristics. To be accurate, the model used during the modeling process must take into consideration the structure and composition of the pattern under analysis as well as structure and composition of material that is elevationally inward of the outermost pattern being analyzed. This is because some of the incident radiation will pass through the pattern into substrate material there-below. It then passes through such material, reflects off of a base substrate, and passes back through the material to be detected and analyzed as part of the reflected radiation from the outermost pattern. Such adds significant complexity and opportunity for error associated with the software modeling, particularly with anticipated circuitry designs that may include tens or a hundred or more layers of various materials and structures beneath the outermost pattern being analyzed.
Additionally, scatterometry analysis typically occurs with respect to a patterned test or target area that is laterally displaced from the substrate area within which actual operative components are being fabricated. For example, integrated circuitry fabrication commonly forms the same circuitry within multiple spaced die areas on a larger substrate also known as a semiconductor wafer. These die areas are separated by what is commonly referred to as kerf, street, or scribe-line area that is ultimately cut-through to separate the finished die areas into singulated die or chips. The scatterometry targets are typically formed within this street area at different x-y locations for the different levels of patterning and correspond with the patterning that occurs at that level with respect to the circuitry being formed in the die areas. The street area within which the scatterometry targets are formed are among the largest open areas on the wafer. This can lead to dishing in the street area during polishing of the wafer. Dishing can result in height differences between the outermost surface of the scatterometry target and the surface of the corresponding pattern in the die areas. This can result in fundamental patterning problems and other processing issues that may make it difficult or impossible to create a scatterometry target which closely mimics the patterning in the die area.
While aspects of the invention were motivated in addressing some of the above issues, the inventions disclosed herein are in no way so-limited unless referred to in a specific claim under analysis.